Unverified Commit 0b9c82eb authored by Athokshay Ashok's avatar Athokshay Ashok Committed by GitHub
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set_property IOSTANDARD LVCMOS33 [get_ports clock]
set_property IOSTANDARD LVCMOS33 [get_ports i_r]
set_property IOSTANDARD LVCMOS33 [get_ports {address[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {address[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {address[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dig[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {index[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {index[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {index[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {position[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {position[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {position[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {position[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {position[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {position[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {position[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {position[0]}]
set_property PACKAGE_PIN E3 [get_ports clock]
set_property PACKAGE_PIN U9 [get_ports i_r]
set_property PACKAGE_PIN V2 [get_ports {address[0]}]
set_property PACKAGE_PIN U2 [get_ports {address[1]}]
set_property PACKAGE_PIN T3 [get_ports {address[2]}]
set_property PACKAGE_PIN N6 [get_ports {position[0]}]
set_property PACKAGE_PIN M6 [get_ports {position[1]}]
set_property PACKAGE_PIN M3 [get_ports {position[2]}]
set_property PACKAGE_PIN N5 [get_ports {position[3]}]
set_property PACKAGE_PIN N2 [get_ports {position[4]}]
set_property PACKAGE_PIN N4 [get_ports {position[5]}]
set_property PACKAGE_PIN L1 [get_ports {position[6]}]
set_property PACKAGE_PIN M1 [get_ports {position[7]}]
set_property PACKAGE_PIN R3 [get_ports {index[0]}]
set_property PACKAGE_PIN P3 [get_ports {index[1]}]
set_property PACKAGE_PIN P4 [get_ports {index[2]}]
set_property PACKAGE_PIN L3 [get_ports {dig[0]}]
set_property PACKAGE_PIN N1 [get_ports {dig[1]}]
set_property PACKAGE_PIN L5 [get_ports {dig[2]}]
set_property PACKAGE_PIN L4 [get_ports {dig[3]}]
set_property PACKAGE_PIN K3 [get_ports {dig[4]}]
set_property PACKAGE_PIN M2 [get_ports {dig[5]}]
set_property PACKAGE_PIN L6 [get_ports {dig[6]}]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library IEEE_Proposed;
use IEEE_Proposed.float_pkg.all;
use work.complex_record.all;
entity eight_point_fft_pipeline_testbench is
-- Port ( );
end eight_point_fft_pipeline_testbench;
architecture Behavioral of eight_point_fft_pipeline_testbench is
component eight_point_fft_pipeline is
Port (
input : in mem;
clk : in std_logic;
output: out mem
);
end component eight_point_fft_pipeline;
COMPONENT clk_gen_sim_0
PORT (
axi_clk_in_0 : IN STD_LOGIC;
axi_rst_in_0_n : IN STD_LOGIC;
axi_clk_0 : OUT STD_LOGIC;
axi_rst_0_n : OUT STD_LOGIC
);
END COMPONENT;
signal xt, yt: mem;
signal clk_out, rst_out : std_logic;
begin
clk_gen: clk_gen_sim_0 port map(axi_clk_in_0=> '1', axi_rst_in_0_n=> '0', axi_clk_0=> clk_out, axi_rst_0_n=> rst_out);
eight_point: eight_point_fft_pipeline port map (
input => xt,
clk=> clk_out,
output => yt);
xt(0).r <= std_logic_vector(to_float(1,8, 23));
xt(0).i <= std_logic_vector(to_float(0,8, 23));
xt(1).r <= std_logic_vector(to_float(0,8, 23));
xt(1).i <= std_logic_vector(to_float(2,8, 23));
xt(2).r <= std_logic_vector(to_float(0,8, 23));
xt(2).i <= std_logic_vector(to_float(0,8, 23));
xt(3).r <= std_logic_vector(to_float(0,8, 23));
xt(3).i <= std_logic_vector(to_float(0,8, 23));
xt(4).r <= std_logic_vector(to_float(0,8, 23));
xt(4).i <= std_logic_vector(to_float(0,8, 23));
xt(5).r <= std_logic_vector(to_float(0,8, 23));
xt(5).i <= std_logic_vector(to_float(0,8, 23));
xt(6).r <= std_logic_vector(to_float(0,8, 23));
xt(6).i <= std_logic_vector(to_float(1,8, 23));
xt(7).r <= std_logic_vector(to_float(1,8, 23));
xt(7).i <= std_logic_vector(to_float(0,8, 23));
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library IEEE_PROPOSED;
use IEEE_PROPOSED.float_pkg.all;
use work.complex_record.all;
entity fft_butterly_testbench is
-- Port ( );
end fft_butterly_testbench;
architecture Behavioral of fft_butterly_testbench is
component fft_butterfly is
Port (
A : in complex;
B : in complex;
W : in complex;
clk : std_logic;
A_comp : out complex;
B_comp : out complex
);
end component fft_butterfly;
COMPONENT clk_gen_sim_0
PORT (
axi_clk_in_0 : IN STD_LOGIC;
axi_rst_in_0_n : IN STD_LOGIC;
axi_clk_0 : OUT STD_LOGIC;
axi_rst_0_n : OUT STD_LOGIC
);
END COMPONENT;
signal At, Bt, Wt, B_compt, A_compt : complex;
signal clk_out, rst_out : std_logic;
begin
clk_gen: clk_gen_sim_0 port map(axi_clk_in_0=> '1', axi_rst_in_0_n=> '0', axi_clk_0=> clk_out, axi_rst_0_n=> rst_out);
fft: fft_butterfly port map(A=>At, B=>Bt, W=>Wt, clk => clk_out, A_comp=>A_compt, B_comp=>B_compt);
At.r <= std_logic_vector(to_float(1.5, 8, 23));
At.i <= std_logic_vector(to_float(0.5, 8, 23));
Bt.r <= std_logic_vector(to_float(2, 8, 23));
Bt.i <= std_logic_vector(to_float(-3, 8, 23));
Wt.r <= std_logic_vector(to_float(0.5, 8, 23));
Wt.i <= std_logic_vector(to_float(0.5, 8, 23));
end Behavioral;
// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:clk_gen_sim:1.0
// IP Revision: 0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
clk_gen_sim_0 your_instance_name (
.axi_clk_in_0(axi_clk_in_0), // input wire axi_clk_in_0
.axi_rst_in_0_n(axi_rst_in_0_n), // input wire axi_rst_in_0_n
.axi_clk_0(axi_clk_0), // output wire axi_clk_0
.axi_rst_0_n(axi_rst_0_n) // output wire axi_rst_0_n
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file clk_gen_sim_0.v when simulating
// the core, clk_gen_sim_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:clk_gen_sim:1.0
-- IP Revision: 0
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT clk_gen_sim_0
PORT (
axi_clk_in_0 : IN STD_LOGIC;
axi_rst_in_0_n : IN STD_LOGIC;
axi_clk_0 : OUT STD_LOGIC;
axi_rst_0_n : OUT STD_LOGIC
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : clk_gen_sim_0
PORT MAP (
axi_clk_in_0 => axi_clk_in_0,
axi_rst_in_0_n => axi_rst_in_0_n,
axi_clk_0 => axi_clk_0,
axi_rst_0_n => axi_rst_0_n
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file clk_gen_sim_0.vhd when simulating
-- the core, clk_gen_sim_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
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// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:clk_gen_sim:1.0
// IP Revision: 0
(* X_CORE_INFO = "clk_gen_sim_v1_0_0_0,Vivado 2019.1.0" *)
(* CHECK_LICENSE_TYPE = "design_1_clk_gen_sim_0_0,clk_gen_sim_v1_0_0_0,{}" *)
(* CORE_GENERATION_INFO = "design_1_clk_gen_sim_0_0,clk_gen_sim_v1_0_0_0,{x_ipProduct=Vivado 2019.1.0,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=clk_gen_sim,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,SYS_CLK0_FREQ=400.000,SYS_CLK1_FREQ=400.000,SYS_CLK2_FREQ=400.000,SYS_CLK3_FREQ=400.000,NUM_OF_AXI_CLK=1,AXI_CLK_0_FREQ=300,AXI_CLK_1_FREQ=300,AXI_CLK_2_FREQ=300,AXI_CLK_3_FREQ=300,AXI_CLK_4_FREQ=300,AXI_CLK_5_FREQ=300,AXI_CLK_6_FREQ=300,AXI_CLK_7_FREQ=300,AXI_CLK_8_FREQ=300,AXI_CLK_9_FREQ=\
300}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
`timescale 1ps/1ps
module clk_gen_sim_0 (
axi_clk_in_0
,axi_rst_in_0_n
,axi_clk_0
,axi_rst_0_n
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXI_CLK_IN_0, ASSOCIATED_RESET axi_rst_in_0_n, FREQ_HZ 300000000, PHASE 0.000, CLK_DOMAIN design_1_axi_clk_in_0_0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 AXI_CLK_IN_0 CLK" *)
input wire axi_clk_in_0;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXI_RST_IN_0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AXI_RST_IN_0_N RST" *)
input wire axi_rst_in_0_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXI_CLK_0, ASSOCIATED_RESET axi_rst_0_n, FREQ_HZ 300000000, PHASE 0.000, CLK_DOMAIN design_1_clk_gen_sim_0_0_axi_clk_0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 AXI_CLK_0 CLK" *)
output wire axi_clk_0;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXI_RST_0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AXI_RST_0_N RST" *)
output wire axi_rst_0_n;
`ifdef MODEL_TECH
`define SIMULATION_MODE
`elsif INCA
`define SIMULATION_MODE
`elsif VCS
`define SIMULATION_MODE
`elsif XILINX_SIMULATOR
`define SIMULATION_MODE
`elsif _VCP
`define SIMULATION_MODE
`endif
`ifndef SIMULATION_MODE
assign axi_clk_0 = axi_clk_in_0;
assign axi_rst_0_n = axi_rst_in_0_n;
`else
//synthesis translate off
clk_gen_sim_v1_0_0 #(
.SYS_CLK0_FREQ(400.000),
.SYS_CLK1_FREQ(400.000),
.SYS_CLK2_FREQ(400.000),
.SYS_CLK3_FREQ(400.000),
.NUM_OF_AXI_CLK(1),
.NUM_OF_RESET(0),
.AXI_CLK_0_FREQ(300),
.AXI_CLK_1_FREQ(300),
.AXI_CLK_2_FREQ(300),
.AXI_CLK_3_FREQ(300),
.AXI_CLK_4_FREQ(300),
.AXI_CLK_5_FREQ(300),
.AXI_CLK_6_FREQ(300),
.AXI_CLK_7_FREQ(300),
.AXI_CLK_8_FREQ(300),
.AXI_CLK_9_FREQ(300)
) inst (
.axi_clk_in_0(axi_clk_in_0)
,.axi_rst_in_0_n(axi_rst_in_0_n)
,.axi_clk_0(axi_clk_0)
,.axi_rst_0_n(axi_rst_0_n)
,.axi_clk_in_1(1'B0)
,.axi_rst_in_1_n(1'B0)
,.axi_clk_1()
,.axi_rst_1_n()
,.axi_clk_in_2(1'B0)
,.axi_rst_in_2_n(1'B0)
,.axi_clk_2()
,.axi_rst_2_n()
,.axi_clk_in_3(1'B0)
,.axi_rst_in_3_n(1'B0)
,.axi_clk_3()
,.axi_rst_3_n()
,.axi_clk_in_4(1'B0)
,.axi_rst_in_4_n(1'B0)
,.axi_clk_4()
,.axi_rst_4_n()
,.axi_clk_in_5(1'B0)
,.axi_rst_in_5_n(1'B0)
,.axi_clk_5()
,.axi_rst_5_n()
,.axi_clk_in_6(1'B0)
,.axi_rst_in_6_n(1'B0)
,.axi_clk_6()
,.axi_rst_6_n()
,.axi_clk_in_7(1'B0)
,.axi_rst_in_7_n(1'B0)
,.axi_clk_7()
,.axi_rst_7_n()
,.axi_clk_in_8(1'B0)
,.axi_rst_in_8_n(1'B0)
,.axi_clk_8()
,.axi_rst_8_n()
,.axi_clk_in_9(1'B0)
,.axi_rst_in_9_n(1'B0)
,.axi_clk_9()
,.axi_rst_9_n()
,.sys_clk0_in_p(1'B0)
,.sys_clk0_in_n(1'B0)
,.sys_clk0_p()
,.sys_clk0_n()
,.sys_clk1_in_p(1'B0)
,.sys_clk1_in_n(1'B0)
,.sys_clk1_p()
,.sys_clk1_n()
,.sys_clk2_in_p(1'B0)
,.sys_clk2_in_n(1'B0)
,.sys_clk2_p()
,.sys_clk2_n()
,.sys_clk3_in_p(1'B0)
,.sys_clk3_in_n(1'B0)
,.sys_clk3_p()
,.sys_clk3_n()
);
//synthesis translate on
`endif
endmodule
//`ifdef MODEL_TECH
// `define SIMULATION_MODE
//`elsif INCA
// `define SIMULATION_MODE
//`elsif VCS
// `define SIMULATION_MODE
//`elsif XILINX_SIMULATOR
// `define SIMULATION_MODE
//`elsif _VCP
// `define SIMULATION_MODE
//`endif
`timescale 1ps/1ps
module clk_gen_sim_v1_0_0 #(
parameter real SYS_CLK0_FREQ = 400.000,
parameter real SYS_CLK1_FREQ = 400.000,
parameter real SYS_CLK2_FREQ = 400.000,
parameter real SYS_CLK3_FREQ = 400.000,
parameter NUM_OF_AXI_CLK = 0,
parameter NUM_OF_RESET = 0,
parameter AXI_CLK_0_FREQ = 300,
parameter AXI_CLK_1_FREQ = 300,
parameter AXI_CLK_2_FREQ = 300,
parameter AXI_CLK_3_FREQ = 300,
parameter AXI_CLK_4_FREQ = 300,
parameter AXI_CLK_5_FREQ = 300,
parameter AXI_CLK_6_FREQ = 300,
parameter AXI_CLK_7_FREQ = 300,
parameter AXI_CLK_8_FREQ = 300,
parameter AXI_CLK_9_FREQ = 300
) (
input sys_clk0_in_p
,input sys_clk0_in_n
,input sys_clk1_in_p
,input sys_clk1_in_n
,input sys_clk2_in_p
,input sys_clk2_in_n
,input sys_clk3_in_p
,input sys_clk3_in_n
,output sys_clk0_p
,output sys_clk0_n
,output sys_clk1_p
,output sys_clk1_n
,output sys_clk2_p
,output sys_clk2_n
,output sys_clk3_p
,output sys_clk3_n
,input axi_clk_in_0
,input axi_rst_in_0_n
,output axi_clk_0
,output axi_rst_0_n
,input axi_clk_in_1
,input axi_rst_in_1_n
,output axi_clk_1
,output axi_rst_1_n
,input axi_clk_in_2
,input axi_rst_in_2_n
,output axi_clk_2
,output axi_rst_2_n
,input axi_clk_in_3
,input axi_rst_in_3_n
,output axi_clk_3
,output axi_rst_3_n
,input axi_clk_in_4
,input axi_rst_in_4_n
,output axi_clk_4
,output axi_rst_4_n
,input axi_clk_in_5
,input axi_rst_in_5_n
,output axi_clk_5
,output axi_rst_5_n
,input axi_clk_in_6
,input axi_rst_in_6_n
,output axi_clk_6
,output axi_rst_6_n
,input axi_clk_in_7
,input axi_rst_in_7_n
,output axi_clk_7