Unverified Commit 93e7e8b5 authored by Athokshay Ashok's avatar Athokshay Ashok Committed by GitHub
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Update and rename README to README.md

parent 9bd79838
#Pipelined 8-Point FFT with ROM
This is a VHDL implementation of a pipelined 8-Point Fast Fourier Transform (FFT) that uses the butterfly architecture. Input data points are stored in a ROM, and outputs are displayed on the seven-segment LCD of the Nexys 4 board. Adder/subtractor and multipleir IPs are used to decrease the DSP slice usage, and clock IPs are used in testbenches when running behavioral simulations.
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