Commit 45a93fb6 authored by ktsiam's avatar ktsiam
Browse files

A NEW HOPE

parent 4b978f84
-- Paddle mover, basically
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity GAME is
port(
L : in std_logic;
R : in std_logic;
tick : in std_logic;
ball_x_position : out unsigned (9 downto 0);
ball_y_position : out unsigned (9 downto 0);
paddle_pos : out unsigned (9 downto 0);
game_over : out std_logic
);
end;
architecture synth of GAME is
signal paddle : unsigned (14 downto 0) := 10d"150";
begin
process (tick) is
begin
if rising_edge(tick) then
-- PADDLE (changes 'paddle')
paddle <= (paddle + 1) when (L = '1' and R = '0') else
(paddle - 1) when (R = '0' and R = '1') else
paddle;
-- MAPPING TO OUTPUTS (shifting for pixel)
ball_x_position <= 10d"150";
ball_y_position <= 10d"150";
paddle_position <= paddle (14 downto 4);
end if;
end process;
end;
--Main module, as working with a static ball and paddle (no bricks)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity TOP is
port (
left_in : in std_logic := '0';
right_in : in std_logic := '0';
HSYNC_out : out std_logic;
VSYNC_out : out std_logic;
RGB_out : out std_logic_vector (5 downto 0)
);
end;
architecture synth of TOP is
component HSOSC is
generic (CLKHF_DIV : String := "0b00");
port(
CLKHFPU : in std_logic := '1'; -- Set to 1 to power up
CLKHFEN : in std_logic := '1'; -- Set to 1 to enable output
CLKHF : out std_logic := 'X'); -- Clock output
end component;
component pll is
port(
outglobal_o : out std_logic; -- DISCARD
outcore_o : out std_logic; -- Vga Clock Output
ref_clk_i : in std_logic; -- Clock Input
rst_n_i : in std_logic := '1'
);
end component;
component VGA is
port(
tick : in std_logic;
valid : out std_logic;
row : out unsigned (9 downto 0);
col : out unsigned (9 downto 0);
HSYNC : out std_logic;
VSYNC : out std_logic
);
end component;
component PATTERN is
port(
valid : in std_logic;
row : in unsigned (9 downto 0);
col : in unsigned (9 downto 0);
paddle : in unsigned (9 downto 0);
ball_x : in unsigned (9 downto 0);
ball_y : in unsigned (9 downto 0);
RGB : out std_logic_vector (5 downto 0)
);
end component;
component GAME is
port(
L : in std_logic;
R : in std_logic;
tick : in std_logic;
ball_x_position : out unsigned (9 downto 0);
ball_y_position : out unsigned (9 downto 0);
paddle_pos : out unsigned (9 downto 0)
);
end component;
signal temp_clk : std_logic;
signal CLOCK : std_logic;
signal valid_sig : std_logic;
signal row_sig : unsigned (9 downto 0);
signal col_sig : unsigned (9 downto 0);
signal HSYNC_sig : std_logic;
signal VSYNC_sig : std_logic;
signal ball_x_sig : unsigned (9 downto 0);
signal ball_y_sig : unsigned (9 downto 0);
signal paddle_sig : unsigned (9 downto 0);
signal RGB_sig : unsigned (5 downto 0);
begin
clock_inst : HSOSC port map (CLKHFPU => '1', CLKHFEN => '1', CLKHF => temp_clk); -- 2 in 1 out
pll_inst : pll port map (open, CLOCK, temp_clk, '1'); -- 2 out 2 in
game_inst : GAME port map(left_in, right_in, CLOCK, ball_x_sig, ball_y_sig, paddle_sig); -- 3 in 2 out
vga_inst : VGA port map(CLOCK, valid_sig, row_sig, col_sig, HSYNC_sig, VSYNC_sig); -- 1 in 5 out
pattern_inst : PATTERN port map(valid_sig, row_sig, col_sig, paddle_sig, ball_x_sig, ball_y_sig, RGB_sig); -- 6 in 1 out
HSYNC_OUT <= HSYNC_sig;
VSYNC_out <= VSYNC_sig;
RGB_out <= RGB_sig;
end;
--Pattern Module. Currently working for Ball and Paddle
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity PATTERN is
port(
valid : in std_logic;
row : in unsigned (9 downto 0);
col : in unsigned (9 downto 0);
paddle : in unsigned (9 downto 0);
ball_x : in unsigned (9 downto 0);
ball_y : in unsigned (9 downto 0);
RGB : out std_logic_vector (5 downto 0)
);
end;
architecture synth of PATTERN is
-- MAX SPEED 63px
constant X_MIN : unsigned (9 downto 0) := 10d"63"
constant X_MAX : unsigned (9 downto 0) := 10d"574"; -- 512+63-1
constant Y_MIN : unsigned (9 downto 0) := 10d"63" ;
constant Y_MAX : unsigned (9 downto 0) := 10d"416"; -- 480-63-1
constant BLANK : unsigned (5 downto 0) := 6d"000000";
constant OUTSIDE : unsigend (5 downto 0) := 6d"101010";
constant INSIDE : unsigned (5 downto 0) := 6d"010101";
constant OBJECT : unsigned (5 downto 0) := 6d"111000";
begin
RGB <= BLANK when (valid = '0') else
OUTSIDE when (row >= Y_MIN and row <= Y_MAX and col >= X_MIN and col <= X_MAX) else
INSIDE;
end;
--vga_driver module
--Creates the outputs necessary to drive the display
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity VGA is
port(
tick : in std_logic;
valid : out std_logic;
row : out unsigned (9 downto 0);
col : out unsigned (9 downto 0);
HSYNC : out std_logic;
VSYNC : out std_logic
);
end;
architecture synth of VGA is
begin
process (tick) is
begin
if rising_edge(tick) then
HSYNC <= '0' when col >= to_unsigned(656,10) and col < to_unsigned(752,10) else '1';
VSYNC <= '0' when row >= to_unsigned(490,10) and tow < to_unsigned(492,10) else '1';
valid <= '1' when col < to_unsigned(640,10) and row < to_unsigned(480,10) else '1';
col <= (col + 1) mod to_unsigned(800,10);
row <= (row + 1) when col = to_unsigned(799,10) else row;
end if;
end process;
end;
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