Commit 70bc7d14 authored by ktsiam's avatar ktsiam
Browse files

making it beautiful

parent b22eb0cc
......@@ -5,139 +5,123 @@ use ieee.math_real.all;
entity GAME is
port(
L1 : in std_logic;
R1 : in std_logic;
U1 : in std_logic;
D1 : in std_logic;
L2 : in std_logic;
R2 : in std_logic;
U2 : in std_logic;
D2 : in std_logic;
tick : in std_logic;
paddle_position_x_1 : out unsigned (9 downto 0);
paddle_position_y_1 : out unsigned (9 downto 0);
paddle_position_x_2 : out unsigned (9 downto 0);
paddle_position_y_2 : out unsigned (9 downto 0)
);
L1 : in std_logic;
R1 : in std_logic;
U1 : in std_logic;
D1 : in std_logic;
L2 : in std_logic;
R2 : in std_logic;
U2 : in std_logic;
D2 : in std_logic;
tick : in std_logic;
paddle_position_x_1 : out unsigned (9 downto 0);
paddle_position_y_1 : out unsigned (9 downto 0);
paddle_position_x_2 : out unsigned (9 downto 0);
paddle_position_y_2 : out unsigned (9 downto 0)
);
end;
architecture synth of GAME is
signal paddlex1 : unsigned (14 downto 0);
signal paddley1 : unsigned (14 downto 0);
signal paddlex2 : unsigned (14 downto 0);
signal paddley2 : unsigned (14 downto 0);
signal little_count : unsigned (11 downto 0) := 12d"0";
signal big_count : unsigned (7 downto 0) := 8d"0";
signal once : std_logic := '0';
signal paddlex1 : unsigned (14 downto 0);
signal paddley1 : unsigned (14 downto 0);
signal paddlex2 : unsigned (14 downto 0);
signal paddley2 : unsigned (14 downto 0);
signal little_count : unsigned (11 downto 0) := 12d"0";
signal big_count : unsigned (7 downto 0) := 8d"0";
signal once : std_logic := '0';
begin
paddle_position_x_1 <= paddlex1 (14 downto 5);
paddle_position_x_2 <= paddlex2 (14 downto 5);
paddle_position_y_1 <= paddley1 (14 downto 5);
paddle_position_y_2 <= paddley2 (14 downto 5);
process (tick) is
begin
if rising_edge(tick) then
little_count <= little_count + 1;
-- PADDLE MOVES
little_count <= little_count + 1;
-- PADDLE MOVES
if little_count = 0 then
big_count <= big_count + 1;
paddlex1 <= (paddlex1 + 1) when (L1 = '1' and R1 = '0') and paddlex1 < 14000 else
(paddlex1 - 1) when (L1 = '0' and R1 = '1') and paddlex1 > 6500 else
paddlex1;
paddley1 <= (paddley1 + 1) when (U1 = '1' and D1 = '0') and paddley1 < 12000 else
(paddley1 - 1) when (U1 = '0' and D1 = '1') and paddley1 > 5000 else
paddley1;
paddlex2 <= (paddlex2 + 1) when (L2 = '1' and R2 = '0') and paddlex2 < 12000 else
(paddlex2 - 1) when (L2 = '0' and R2 = '1') and paddlex2 > 5000 else
paddlex2;
paddley2 <= (paddley2 + 1) when (U2 = '1' and D2 = '0') and paddley2 < 14000 else
(paddley2 - 1) when (U2 = '0' and D2 = '1') and paddley2 > 6500 else
paddley2;
-- BALL MOVES
if big_count = 0 then
if once = '0' then -- This happens once
once <= '1';
paddlex1 <= 15d"4800";
paddley1 <= 15d"5000";
paddlex2 <= 15d"5000";
paddley2 <= 15d"5200";
end if;
if paddlex1 = 14000 or paddlex1 = 6500 or paddley1 = 5000 or
(paddlex1 > 9600 and paddlex1 < 9920 and paddley1 < 6400 and paddley1 > 4800) --1
or (paddley1 > 9920 and paddley1 < 10240 and paddlex1 > 8000 and paddlex1 < 13120)--2
or (paddley1 > 8320 and paddley1 < 8640 and paddlex1 > 6400 and paddlex1 < 8000)--3
or (paddley1 > 6080 and paddley1 < 6400 and paddlex1 > 11520 and paddlex1 < 14400)--4
big_count <= big_count + 1;
paddlex1 <= (paddlex1 + 1) when (L1 = '1' and R1 = '0') and paddlex1 < 14000 else
(paddlex1 - 1) when (L1 = '0' and R1 = '1') and paddlex1 > 6500 else
paddlex1;
paddley1 <= (paddley1 + 1) when (U1 = '1' and D1 = '0') and paddley1 < 12000 else
(paddley1 - 1) when (U1 = '0' and D1 = '1') and paddley1 > 5000 else
paddley1;
paddlex2 <= (paddlex2 + 1) when (L2 = '1' and R2 = '0') and paddlex2 < 12000 else
(paddlex2 - 1) when (L2 = '0' and R2 = '1') and paddlex2 > 5000 else
paddlex2;
paddley2 <= (paddley2 + 1) when (U2 = '1' and D2 = '0') and paddley2 < 14000 else
(paddley2 - 1) when (U2 = '0' and D2 = '1') and paddley2 > 6500 else
paddley2;
-- BALL MOVES
if big_count = 0 then
if once = '0' then -- This happens once
once <= '1';
paddlex1 <= 15d"4800";
paddley1 <= 15d"5000";
paddlex2 <= 15d"5000";
paddley2 <= 15d"5200";
end if;
if paddlex1 = 14000 or paddlex1 = 6500 or paddley1 = 5000 or
(paddlex1 > 9600 and paddlex1 < 9920 and paddley1 < 6400 and paddley1 > 4800) --1
or (paddley1 > 9920 and paddley1 < 10240 and paddlex1 > 8000 and paddlex1 < 13120)--2
or (paddley1 > 8320 and paddley1 < 8640 and paddlex1 > 6400 and paddlex1 < 8000)--3
or (paddley1 > 6080 and paddley1 < 6400 and paddlex1 > 11520 and paddlex1 < 14400)--4
or (paddley1 > 8320 and paddley1 < 10240 and paddlex1 > 8960 and paddlex1 < 9280)--5
or (paddley1 > 8640 and paddley1 < 10240 and paddlex1 > 11520 and paddlex1 < 11840)--6
or (paddley1 > 6080 and paddley1 < 7360 and paddlex1 > 11520 and paddlex1 < 11840)--7
or (paddley1 > 7040 and paddley1 < 7360 and paddlex1 > 11520 and paddlex1 < 13120)--8
or (paddley1 > 7040 and paddley1 < 8000 and paddlex1 > 12800 and paddlex1 < 13120)--9
or (paddley1 > 8640 and paddley1 < 8960 and paddlex1 > 10560 and paddlex1 < 11840)--10
or (paddley1 > 6400 and paddley1 < 8960 and paddlex1 > 10560 and paddlex1 < 10880)--11
or (paddley1 > 7040 and paddley1 < 7360 and paddlex1 > 8000 and paddlex1 < 10880)--12
or (paddley1 > 6080 and paddley1 < 7360 and paddlex1 > 8000 and paddlex1 < 8320)--13
or (paddley1 > 3200 and paddley1 < 5120 and paddlex1 > 12800 and paddlex1 < 13120)--14
then
paddlex1 <= 15d"7000";
paddley1 <= 15d"12000";
end if;
if paddley2 = 14000 or paddley2 = 6500 or paddlex2 = 5000 or
(paddley2 > 9600 and paddley2 < 9920 and paddlex2 < 6400 and paddlex2 > 4800) --1
or (paddlex2 > 9920 and paddlex2 < 10240 and paddley2 > 8000 and paddley2 < 13120)--2
or (paddlex2 > 8320 and paddlex2 < 8640 and paddley2 > 6400 and paddley2 < 8000)--3
or (paddlex2 > 6080 and paddlex2 < 6400 and paddley2 > 11520 and paddley2 < 14400)--4
or (paddley1 > 8320 and paddley1 < 10240 and paddlex1 > 8960 and paddlex1 < 9280)--5
or (paddley1 > 8640 and paddley1 < 10240 and paddlex1 > 11520 and paddlex1 < 11840)--6
or (paddley1 > 6080 and paddley1 < 7360 and paddlex1 > 11520 and paddlex1 < 11840)--7
or (paddley1 > 7040 and paddley1 < 7360 and paddlex1 > 11520 and paddlex1 < 13120)--8
or (paddley1 > 7040 and paddley1 < 8000 and paddlex1 > 12800 and paddlex1 < 13120)--9
or (paddley1 > 8640 and paddley1 < 8960 and paddlex1 > 10560 and paddlex1 < 11840)--10
or (paddley1 > 6400 and paddley1 < 8960 and paddlex1 > 10560 and paddlex1 < 10880)--11
or (paddley1 > 7040 and paddley1 < 7360 and paddlex1 > 8000 and paddlex1 < 10880)--12
or (paddley1 > 6080 and paddley1 < 7360 and paddlex1 > 8000 and paddlex1 < 8320)--13
or (paddley1 > 3200 and paddley1 < 5120 and paddlex1 > 12800 and paddlex1 < 13120)--14
then
paddlex1 <= 15d"7000";
paddley1 <= 15d"12000";
end if;
if paddley2 = 14000 or paddley2 = 6500 or paddlex2 = 5000 or
(paddley2 > 9600 and paddley2 < 9920 and paddlex2 < 6400 and paddlex2 > 4800) --1
or (paddlex2 > 9920 and paddlex2 < 10240 and paddley2 > 8000 and paddley2 < 13120)--2
or (paddlex2 > 8320 and paddlex2 < 8640 and paddley2 > 6400 and paddley2 < 8000)--3
or (paddlex2 > 6080 and paddlex2 < 6400 and paddley2 > 11520 and paddley2 < 14400)--4
or (paddlex2 > 8320 and paddlex2 < 10240 and paddley2 > 8960 and paddley2 < 9280)--5
or (paddlex2 > 8640 and paddlex2 < 10240 and paddley2 > 11520 and paddley2 < 11840)--6
or (paddlex2 > 6080 and paddlex2 < 7360 and paddley2 > 11520 and paddley2 < 11840)--7
or (paddlex2 > 7040 and paddlex2 < 7360 and paddley2 > 11520 and paddley2 < 13120)--8
or (paddlex2 > 7040 and paddlex2 < 8000 and paddley2 > 12800 and paddley2 < 13120)--9
or (paddlex2 > 8640 and paddlex2 < 8960 and paddley2 > 10560 and paddley2 < 11840)--10
or (paddlex2 > 6400 and paddlex2 < 8960 and paddley2 > 10560 and paddley2 < 10880)--11
or (paddlex2 > 7040 and paddlex2 < 7360 and paddley2 > 8000 and paddley2 < 10880)--12
or (paddlex2 > 6080 and paddlex2 < 7360 and paddley2 > 8000 and paddley2 < 8320)--13
or (paddlex2 > 3200 and paddlex2 < 5120 and paddley2 > 12800 and paddley2 < 13120)--14
then
paddley2 <= 15d"7000";
paddlex2 <= 15d"12000";
end if;
--if paddlex1 > 9600 and paddlex1 < 9920 and paddley1 < 4800 and paddley1 > 6400 then
--or (row > 150 and row < 200 and col > 300 and col < 310)--1
--or (row > 310 and row < 320 and col > 250 and col < 410)--2
--or (row > 260 and row < 270 and col > 200 and col < 250)--3
--or (row > 190 and row < 200 and col > 360 and col < 450)--4
end if;
end if;
or (paddlex2 > 8320 and paddlex2 < 10240 and paddley2 > 8960 and paddley2 < 9280)--5
or (paddlex2 > 8640 and paddlex2 < 10240 and paddley2 > 11520 and paddley2 < 11840)--6
or (paddlex2 > 6080 and paddlex2 < 7360 and paddley2 > 11520 and paddley2 < 11840)--7
or (paddlex2 > 7040 and paddlex2 < 7360 and paddley2 > 11520 and paddley2 < 13120)--8
or (paddlex2 > 7040 and paddlex2 < 8000 and paddley2 > 12800 and paddley2 < 13120)--9
or (paddlex2 > 8640 and paddlex2 < 8960 and paddley2 > 10560 and paddley2 < 11840)--10
or (paddlex2 > 6400 and paddlex2 < 8960 and paddley2 > 10560 and paddley2 < 10880)--11
or (paddlex2 > 7040 and paddlex2 < 7360 and paddley2 > 8000 and paddley2 < 10880)--12
or (paddlex2 > 6080 and paddlex2 < 7360 and paddley2 > 8000 and paddley2 < 8320)--13
or (paddlex2 > 3200 and paddlex2 < 5120 and paddley2 > 12800 and paddley2 < 13120)--14
then
paddley2 <= 15d"7000";
paddlex2 <= 15d"12000";
end if;
end if;
end if;
end if;
end process;
end;
......@@ -6,15 +6,15 @@ entity TOP is
port (
left_in_1 : in std_logic := '0';
right_in_1 : in std_logic := '0';
up_in_1 : in std_logic := '0';
down_in_1 : in std_logic := '0';
left_in_2 : in std_logic := '0';
up_in_1 : in std_logic := '0';
down_in_1 : in std_logic := '0';
left_in_2 : in std_logic := '0';
right_in_2 : in std_logic := '0';
up_in_2 : in std_logic := '0';
down_in_2 : in std_logic := '0';
HSYNC_out : out std_logic;
VSYNC_out : out std_logic;
RGB_out : out std_logic_vector (5 downto 0)
up_in_2 : in std_logic := '0';
down_in_2 : in std_logic := '0';
HSYNC_out : out std_logic;
VSYNC_out : out std_logic;
RGB_out : out std_logic_vector (5 downto 0)
);
end;
......@@ -34,7 +34,7 @@ architecture synth of TOP is
outcore_o : out std_logic; -- Vga Clock Output
ref_clk_i : in std_logic; -- Clock Input
rst_n_i : in std_logic := '1'
);
);
end component;
component VGA is
......@@ -45,7 +45,7 @@ architecture synth of TOP is
col : out unsigned (9 downto 0);
HSYNC : out std_logic;
VSYNC : out std_logic
);
);
end component;
component PATTERN is
......@@ -54,43 +54,43 @@ architecture synth of TOP is
row : in unsigned (9 downto 0);
col : in unsigned (9 downto 0);
paddlex1 : in unsigned (9 downto 0);
paddley1 : in unsigned (9 downto 0);
paddley1 : in unsigned (9 downto 0);
paddlex2 : in unsigned (9 downto 0);
paddley2 : in unsigned (9 downto 0);
paddley2 : in unsigned (9 downto 0);
RGB : out std_logic_vector (5 downto 0)
);
end component;
component GAME is
port(
L1 : in std_logic;
R1 : in std_logic;
U1 : in std_logic;
D1 : in std_logic;
L2 : in std_logic;
R2 : in std_logic;
U2 : in std_logic;
D2 : in std_logic;
tick : in std_logic;
L1 : in std_logic;
R1 : in std_logic;
U1 : in std_logic;
D1 : in std_logic;
L2 : in std_logic;
R2 : in std_logic;
U2 : in std_logic;
D2 : in std_logic;
tick : in std_logic;
paddle_position_x_1 : out unsigned (9 downto 0);
paddle_position_y_1 : out unsigned (9 downto 0);
paddle_position_x_2 : out unsigned (9 downto 0);
paddle_position_y_2 : out unsigned (9 downto 0)
paddle_position_y_1 : out unsigned (9 downto 0);
paddle_position_x_2 : out unsigned (9 downto 0);
paddle_position_y_2 : out unsigned (9 downto 0)
);
end component;
signal temp_clk : std_logic;
signal CLOCK : std_logic;
signal CLOCK : std_logic;
signal valid_sig : std_logic;
signal row_sig : unsigned (9 downto 0);
signal col_sig : unsigned (9 downto 0);
signal row_sig : unsigned (9 downto 0);
signal col_sig : unsigned (9 downto 0);
signal HSYNC_sig : std_logic;
signal VSYNC_sig : std_logic;
signal paddle_x1 : unsigned (9 downto 0);
signal paddle_y1 : unsigned (9 downto 0);
signal paddle_x2 : unsigned (9 downto 0);
......@@ -103,7 +103,9 @@ begin
clock_inst : HSOSC port map (CLKHFPU => '1', CLKHFEN => '1', CLKHF => temp_clk); -- 2 in 1 out
pll_inst : pll port map (open, CLOCK, temp_clk, '1'); -- 2 out 2 in
game_inst : GAME port map(left_in_1, right_in_1, up_in_1, down_in_1, left_in_2, right_in_2, up_in_2, down_in_2, CLOCK, paddle_x1, paddle_y1, paddle_x2, paddle_y2); -- 3 in 2 out
game_inst : GAME port map(left_in_1, right_in_1, up_in_1, down_in_1,
left_in_2, right_in_2, up_in_2, down_in_2,
CLOCK, paddle_x1, paddle_y1, paddle_x2, paddle_y2);
vga_inst : VGA port map(CLOCK, valid_sig, row_sig, col_sig, HSYNC_sig, VSYNC_sig); -- 1 in 5 out
pattern_inst : PATTERN port map(valid_sig, row_sig, col_sig, paddle_x1, paddle_y1, paddle_x2, paddle_y2, RGB_sig); -- 6 in 1 out
......
......@@ -8,9 +8,9 @@ entity PATTERN is
row : in unsigned (9 downto 0);
col : in unsigned (9 downto 0);
paddlex1 : in unsigned (9 downto 0);
paddley1 : in unsigned (9 downto 0);
paddlex2 : in unsigned (9 downto 0);
paddley2 : in unsigned (9 downto 0);
paddley1 : in unsigned (9 downto 0);
paddlex2 : in unsigned (9 downto 0);
paddley2 : in unsigned (9 downto 0);
RGB : out std_logic_vector (5 downto 0)
);
end;
......@@ -19,42 +19,30 @@ architecture synth of PATTERN is
begin
--RGB <= INSIDE when valid = '1' else BLANK;
--RGB <= "001011" when valid = '1' and row > 200 and row < 400 and col > 200 and col < 300 else "011101";
--RGB <= OUTSIDE when row < 10d"640" and row > 10d"100" and col < 10d"480" and col > 10d"100"else BLANK;
--RGB <= BLANK when (valid = '0') else
--OUTSIDE when (row >= Y_MIN and row <= Y_MAX and col >= X_MIN and col <= X_MAX) else
--INSIDE;
RGB <= "011001" when (col < (paddlex1 + 15) and col > paddlex1 - 1 and row < paddley1 + 10 and row > paddley1 - 1) else
"000111" when (row < (paddlex2 + 15) and row > paddlex2 - 1 and col < paddley2 + 10 and col > paddley2 - 1) else
"111111" when (row > 150 and row < 160 and col > 200 and col < 410)--top border
or (row > 350 and row < 360 and col > 240 and col < 450)--bottom border
or (row > 150 and row < 360 and col > 200 and col < 210)--left border
or (row > 100 and row < 360 and col > 440 and col < 450)--right border
or (row > 150 and row < 200 and col > 300 and col < 310)--1
or (row > 310 and row < 320 and col > 250 and col < 410)--2
or (row > 260 and row < 270 and col > 200 and col < 250)--3
or (row > 190 and row < 200 and col > 360 and col < 450)--4
or (row > 260 and row < 320 and col > 280 and col < 290)--5
or (row > 270 and row < 320 and col > 360 and col < 370)--6
or (row > 190 and row < 230 and col > 360 and col < 370)--7
or (row > 220 and row < 230 and col > 360 and col < 410)--8
or (row > 220 and row < 250 and col > 400 and col < 410)--9
or (row > 270 and row < 280 and col > 330 and col < 370)--10
or (row > 200 and row < 280 and col > 330 and col < 340)--11
or (row > 220 and row < 230 and col > 250 and col < 340)--12
or (row > 190 and row < 230 and col > 250 and col < 260)--13
or (row > 100 and row < 160 and col > 400 and col < 410)--14
RGB <= "011001" when (col < (paddlex1 + 15) and col > paddlex1 - 1 and row < paddley1 + 10 and row > paddley1 - 1) else
"000111" when (row < (paddlex2 + 15) and row > paddlex2 - 1 and col < paddley2 + 10 and col > paddley2 - 1) else
"111111" when (row > 150 and row < 160 and col > 200 and col < 410)--top border
or (row > 350 and row < 360 and col > 240 and col < 450)--bottom border
or (row > 150 and row < 360 and col > 200 and col < 210)--left border
or (row > 100 and row < 360 and col > 440 and col < 450)--right border
or (row > 150 and row < 200 and col > 300 and col < 310)--1
or (row > 310 and row < 320 and col > 250 and col < 410)--2
or (row > 260 and row < 270 and col > 200 and col < 250)--3
or (row > 190 and row < 200 and col > 360 and col < 450)--4
else "000000";
or (row > 260 and row < 320 and col > 280 and col < 290)--5
or (row > 270 and row < 320 and col > 360 and col < 370)--6
or (row > 190 and row < 230 and col > 360 and col < 370)--7
or (row > 220 and row < 230 and col > 360 and col < 410)--8
or (row > 220 and row < 250 and col > 400 and col < 410)--9
or (row > 270 and row < 280 and col > 330 and col < 370)--10
or (row > 200 and row < 280 and col > 330 and col < 340)--11
or (row > 220 and row < 230 and col > 250 and col < 340)--12
or (row > 190 and row < 230 and col > 250 and col < 260)--13
or (row > 100 and row < 160 and col > 400 and col < 410)--14
else "000000";
end;
......@@ -11,22 +11,22 @@ entity VGA is
col : out unsigned (9 downto 0) := 10d"0";
HSYNC : out std_logic;
VSYNC : out std_logic
);
);
end;
architecture synth of VGA is
begin
horz_pos_counter : process(tick)
begin
horz_pos_counter : process(tick)
begin
if(rising_edge(tick)) then
col <= 10d"0" when col = 799 else (col + 1);
row <= 10d"0" when col = 799 and row = 524 else
(row + 1) when col = 799;
HSYNC <= '0' when col > 655 and col < 752 else '1';
VSYNC <= '0' when row > 489 and row < 492 else '1';
valid <= '1' when row < 480 and col < 640 else '0';
col <= 10d"0" when col = 799 else (col + 1);
row <= 10d"0" when col = 799 and row = 524 else
(row + 1) when col = 799;
HSYNC <= '0' when col > 655 and col < 752 else '1';
VSYNC <= '0' when row > 489 and row < 492 else '1';
valid <= '1' when row < 480 and col < 640 else '0';
end if;
end process;
end process;
end;
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