Commit 70bc7d14 authored by ktsiam's avatar ktsiam
Browse files

making it beautiful

parent b22eb0cc
......@@ -120,23 +120,7 @@ begin
paddley2 <= 15d"7000";
paddlex2 <= 15d"12000";
end if;
--if paddlex1 > 9600 and paddlex1 < 9920 and paddley1 < 4800 and paddley1 > 6400 then
--or (row > 150 and row < 200 and col > 300 and col < 310)--1
--or (row > 310 and row < 320 and col > 250 and col < 410)--2
--or (row > 260 and row < 270 and col > 200 and col < 250)--3
--or (row > 190 and row < 200 and col > 360 and col < 450)--4
end if;
end if;
end if;
end process;
......
......@@ -103,7 +103,9 @@ begin
clock_inst : HSOSC port map (CLKHFPU => '1', CLKHFEN => '1', CLKHF => temp_clk); -- 2 in 1 out
pll_inst : pll port map (open, CLOCK, temp_clk, '1'); -- 2 out 2 in
game_inst : GAME port map(left_in_1, right_in_1, up_in_1, down_in_1, left_in_2, right_in_2, up_in_2, down_in_2, CLOCK, paddle_x1, paddle_y1, paddle_x2, paddle_y2); -- 3 in 2 out
game_inst : GAME port map(left_in_1, right_in_1, up_in_1, down_in_1,
left_in_2, right_in_2, up_in_2, down_in_2,
CLOCK, paddle_x1, paddle_y1, paddle_x2, paddle_y2);
vga_inst : VGA port map(CLOCK, valid_sig, row_sig, col_sig, HSYNC_sig, VSYNC_sig); -- 1 in 5 out
pattern_inst : PATTERN port map(valid_sig, row_sig, col_sig, paddle_x1, paddle_y1, paddle_x2, paddle_y2, RGB_sig); -- 6 in 1 out
......
......@@ -19,12 +19,6 @@ architecture synth of PATTERN is
begin
--RGB <= INSIDE when valid = '1' else BLANK;
--RGB <= "001011" when valid = '1' and row > 200 and row < 400 and col > 200 and col < 300 else "011101";
--RGB <= OUTSIDE when row < 10d"640" and row > 10d"100" and col < 10d"480" and col > 10d"100"else BLANK;
--RGB <= BLANK when (valid = '0') else
--OUTSIDE when (row >= Y_MIN and row <= Y_MAX and col >= X_MIN and col <= X_MAX) else
--INSIDE;
RGB <= "011001" when (col < (paddlex1 + 15) and col > paddlex1 - 1 and row < paddley1 + 10 and row > paddley1 - 1) else
"000111" when (row < (paddlex2 + 15) and row > paddlex2 - 1 and col < paddley2 + 10 and col > paddley2 - 1) else
......@@ -50,11 +44,5 @@ begin
or (row > 190 and row < 230 and col > 250 and col < 260)--13
or (row > 100 and row < 160 and col > 400 and col < 410)--14
else "000000";
end;
......@@ -17,8 +17,8 @@ end;
architecture synth of VGA is
begin
horz_pos_counter : process(tick)
begin
horz_pos_counter : process(tick)
begin
if(rising_edge(tick)) then
col <= 10d"0" when col = 799 else (col + 1);
row <= 10d"0" when col = 799 and row = 524 else
......@@ -28,5 +28,5 @@ begin
valid <= '1' when row < 480 and col < 640 else '0';
end if;
end process;
end process;
end;
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